Cy630r 315 MHz Sop8 Integrated Circuit Wireless RF Receiver Chip IC

• Customization: Available
• Conductive Type: Unipolar Integrated Circuit
• Integration: GSI
• Model NO.: CY630R
• Shape: DIP
• Frequency: 315 MHz
• Sensitivity: -114dBm
• Data Rate: up to 10kbps
• Current: 4.3mA
• Voltage: 2.2~5.5V
• Ambient Temperature: -20° C to 70° C
• Packaging: Sop8
• Lead Time: 3 Weeks After Receiving Payment
• Ship by: DHL/FedEx/UPS
• MOQ: 100PCS
• Transport Package: Reel
• Trademark: CY
• Origin: China
• HS Code: 8542399000
• Production Capacity: 200000PCS/Year

Product Description

General Description

The CY630R is a compact, fully integrated OOK/ASK receiver for 433.92 MHz frequency band. It requires few external components. The CY620R consists of a low-noise amplifier (LNA), image-rejection mixer (IRM), built-in channel-select filter (CSF), OOK/ASK demodulator, data filter, and data slicing comparator. The local oscillator (LO) sub-system incorporates a monolithic VCO, ÷32 feedback divider, loop filter and fast start-up reference oscillator to form a complete phase-locked loop-based frequency synthesizer for single channel applications.

The CY630R is available in an 8-pin SOP package and is specified over the temperature range from -20 to +70 °C.


 Features

1. Normal operating of 4.3 mA at 315 MHz
2. Requires few external components
3. Achieves sensitivity of -114 dBm (peak ASK signal level)
4. Supply voltage range: 2.2 to 5.5 V
5. Supports data rates up to 10 Kb/s
6. Wide input dynamic range with automatic gain control handling
7. Image-rejection ratio of 25 dB

Applications

1. Automotive Remote Keyless Entry (RKE)
2. Remote control
3. Garage door and gate openers
4. Suitable for applications that must adhere to either the European ETSI-300-220 or the North American FCC (Part 15) regulatory standards

 

Pin Configuration

Pin Description

Pin No.	Pin Name	I/O	Description
1	VSS	G	Ground
2	ANT	I	RF input connected to antenna via a matching network
3	VREG	P	Regulated core voltage
4	VDD5	P	5 V regulator input
5	EN	I	Chip enable (tie HIGH to enable the chip)
6	DO	O	Data output
7	CTH	I/O	Connection for data slicing threshold capacitor
8	XIN	I	Reference oscillator input